register toggles when all it's inputs are zero!

This is one of my wieredest experiences ever! the logic is very simple. regsiter a pulse signal until gets cleared by the master. The output is toggled when all the inputs are zero!!! I can see this in signaltap

always @(posedge clk, negedge reset_n_int)

begin:reg_block

if (reset_n_int==1'b0)

par_err_level <=1'b0;

else

if(clear==1'b1)

par_err_level <=1'b0; //clear the parity when clr register is written

else

begin

if (par_err==1'b1)

par_err_level <=1'b1;

else //looks ugly. added because of parity error issue in the build. no need to this!

par_err_level <= par_err_level;

end

end