Regarding displaying Cache Memory access register in Signal Tap II Logic Analyzer

Hello,

I am working on a project and I have read and see how the processor is accessing cache memory. Like cache position, flag bit, whether it is a miss or hit and other information of this sort of. I am using Altera Cyclone III board for implementing my design and using Signal Tap II Logic Analyzer to analyze the cache.

I am not able to find out how can I monitor cache using this. Which register to tap into in the tool to see such information.

Thanks,

Arun