Recovering 10-bit LVDS data and Embedded CLK

162 Mbps sounds rather gentle.

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The other assumption is that proper phase alignment of the CLK on the receive side with the incoming data stream is not critical since all clocks are synchronous.

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That's what I meant with availability of a source synchronous reference.

With reconfigurable PLLs in Cyclone III, your basically able to adjust a receiver PLL to incoming data without a dedicated DPA circuit. But you won't be able to track a shifting data phase.