Recovering 10-bit LVDS data and Embedded CLK

Thanks for the note. To put things in context, the incoming serial data stream (162Mbps) is from an imager, so I have a frame sync pattern that I can use as a flag. I was thinking of having some logic before the LVDS receiver that would enable the receiver once this sync pattern was detected. I was thinking of using an external PLL block (outside ALTLVDS megafunction) to provide the CLK for the LVDS drivers on the imager chip as well as the CLK for the sync detection logic and LVDS receiver, so all clocks are synchronous. The LVDS receiver is 1:12 (but real data is 10-bits) and the slow clock to latch the outputs is also provided by the PLL.

The above makes two assumptions. Once I define an I/O as LVDS it converts into a serial data stream so the logic used to detect the sync pattern assumes a single-channel input bit stream is available. The other assumption is that proper phase alignment of the CLK on the receive side with the incoming data stream is not critical since all clocks are synchronous.