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Altera_Forum
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17 years ago

Recovering 10-bit LVDS data and Embedded CLK

I'm trying to use the Cyclone III starter kit to implement a serial adapter board that has as input a single-channel continuous LVDS data stream with 12-bit words (10 bit data and start and stop bit ...
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Altera_Forum
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17 years ago

I don't think, that any Altera FPGA is able to decode National embedded clock LVDS without an additional reference clock. As a disadvantage compared to 8b/10b coding, the protocol depends on an additional sync channel. Altera is supporting 8b/10b encoding with Arria GX and various Stratix GX families

If the source synchronous reference clock is available, Stratix/Arria DPA feature would be able to adjust the receiver phase according to the embedded clock.