Records in sensitivity lists

As frequently mentioned in the forum, sensitivity lists are basically ignored in synthesis, although Quartus warns about missing entries. Simply, combinational processes are translated to combinational logic and clocked processes to FF based logic. They neither need a trigger to do their work.

But it's different in simulation with full-featured simulators as ModelSim. They interpret the VHDL text and usually ignore events at signals, that aren't included in the sensitivity list. The Quartus warnings should e understood to keep the integrity of simulation and synthesis.

Also in simulation, it doesn't harm to have unnecessary sensivity list entries, except possibly increasing simulation time.