Recommended procedure for FPGA clock forwarding

Hello,

I have an FPGA clock coming into my design.

I want to simply send this clock using another pin.

From working with other vendors - I learned that the recommended practice is to use an Output DDR Flip Flop for that purpose - as described in this link :

https://forums.xilinx.com/t5/Timing-Analysis/Why-ODDR-for-forwarded-clock/td-p/756737

Is this also the recommended practice for Intel FPGAs ?