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Altera_Forum's avatar
Altera_Forum
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12 years ago

$readmemb task trouble

Hi Guys, I have a problem with $readmemb :( This is my code:

`timescale 1ns/100ps

`include "rom_sin_vec.txt"

module ROM_sin

(

input clk, rst,

input [10:0] addr,

output reg [11:0] data

);

reg [10:0] temp;

integer i;

reg [11:0] RAM_2048_12BIT [2047:0];

$readmemb ("rom_sin_vec.txt", RAM_2048_12BIT);

always @ (posedge clk or negedge rst)

begin

if (!rst)

data <= 12'b0;

else

if (clk)

begin

temp[10:0] = addr;

data = RAM_2048_12BIT[temp];

end

end

endmodule

And this is my txt file content

12'b000000000000

12'b000000000110

...

12'b111111111001

And when I compile my project, I got this error:

** Error: rom_sin_vec.txt(1): near "12": syntax error, unexpected "INTEGER NUMBER", expecting "class"

I'm using Modelsim-Altera Starter Edition, Version 6.5b

Who can tell me why this error occurs and how to fix it :( thank you so much

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Try removing the 12'b from the file.

    I've always just had the binary digits one data word per line. (In this case 12 binary digits)

    Pete
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I think remove "12'b" will work.

    my project use hex data:

    $readmemh("cos.txt", rom);

    cos.txt:

    7fff

    7ff9

    7fe6

    7fc7

    7f9a

    7f62

    7f1c
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    You should not have `include "rom_sin_vec.txt" in your code. It does not get compiled as Verilog syntax and you do not put 12'b in front of each word. The $readmemb task will read the file as binary text.