Reading SPI data. The VHDL synchronize problem?

Thank you guys :)

That really helps!

My program's working now but seems like I cannot make it the way you told me to not use the SPI clock to shift the register. I tried but my programming skills cannot help with that. I'm still stuck with the timing issue. Or maybe the main clock is not enough. Or whatever happens with FPGA structure.

MTM: I tried so simulate the SPI clock but I have to use the CS signal to synchronize it. Maybe because of that that I cannot generate it correctly. Then I think the problem is that the CS signal causing timing issue.

My solution is then, use a higher clock speed as Tricky said to deal with it. And anything works like a charm :D

process(SPI_SCLK) -- It still works with this small project

begin

if rising_edge(SPI_SCLK) then

sdata_reg <= sdata_reg(len_SPI-2 downto 0) & SPI_DIO;

end if;

end process;

process(RESET,CLOCK_50)

begin

if RESET = '1' then

nSPIstate <= initial;

elsif rising_edge(CLOCK_50) then

nSPIstate <= SPIstate;

if SPIstate = ready then

DATA_REG_O <= not(sdata_reg(len_SPI-1)) & sdata_reg(len_SPI-2 downto 0);

end if;

end if;

end process;

process(SPIstate,SPI_CS)

begin -- To detect the middle of the CS signal (not just rising or falling which causes timing issue)

end process;