Honored Contributor
Honored ContributorHi,
I think the best way is to synchronize everything that is running on the chip to one central clock, but assuming this SPI function does not have any interface to other VHDL modules, you can also assign a different clock to this "SPI section" of the FPGA. Just as a reminder - if you intend to use different clocks, you either need to ensure the chip has the capability of a second clock distribution network or the second clock can be routed by normal cell interconnects (which would at least lower the max. frequency). If the "SPI module" interfaces with the other logic on the chip (e.g. the "sdata_reg" is generated by other logic you need to ensure that sdata_reg cannot change (as being synchronized to another clock) than the SPI-related signals or you can get messed up readings. the issue with changing information is also most likely causing your troubles, as your code does not ensure any timing constraints between the SPI_CLK refernced part and the SPI_CS related one. Addtionally any glitch on the signal will trigger the code and that causes further problems... all of this "real life" stuff is not within your simulation as I assume the timing between SPI_CS and SPI_CLK is ideal like the signals do not have any glitches etc... As tricky already mentioned the best is to synchronize all signals like SPI_CS and SPI_CLK to System clock and run the code as a System clock depending process.. Defined a internal Signal like iSPI_CLK that is within the System clock process updated with SPI_CLK provides an Option ot detect rising and falling edges of the Signal by comparing SPI_CLK and iSPI_CLK... HTH
