Reading output signals feature in VHDL-2008 & Quartus

I have issue with reading outputs in VHDL-2008 code with Quartus. I made simple example which reads output signals inside process. Then i set VHDL standard to VHDL-2008 (in file properties as well as in global project settings). Compilation error appears:

Error (10309): VHDL Interface Declaration error in vhdl2008.vhd(16): interface object "q" of mode out cannot be read. Change object mode to buffer.

library ieee;
use ieee.std_logic_1164.all;
entity vhdl2008 is
port (clk : in std_logic;
       q: out std_logic := '0');
end entity;
architecture rtl of vhdl2008 is
begin
process(clk)
begin
    if rising_edge(clk) then
        q <= not q;
    end if;
end process;
end rtl;