Timing models don't match measured delays

So, with this design, I can control the placement of the two registers sta_test1 and sta_test2 to get different internal propagation delays from clock to pin. At first I actually ensured once and for all that the clock skew was small, and only considered the clock to output paths. I have now checked the clock skew for all models and cases and it is never more than a few ps. I calibrate the setup by placing both registers in the same ALM, which results in almost equal propagation delay to both outputs, within 100 ps for all OCs.

Then I place the two registers in different ALMs. I let sta_test1 stay in X79,Y328 and move sta_test2 to X350,Y328. I run path analysis in the TA with the following command:

report_path -rise_to [get_ports {master_tod_top_0_pulse_per_second master_tod_top_0_pulse_per_second_raw}] -npaths 10 -panel_name {Report Path} -split_by_corner

The -rise_to is because I'm only interested in and measuring the rising edges. Then I take the reported propagation delay for the two pins and subtract one from the other, for each OC.

Now I should mention that I have recently revised my measurement methodology, the oscilloscope I was using turned out to do bad averaging of channel to channel delay. Visually averaging it on the display resulted in a higher number. Switching to using a time and frequency counter and adjusting the trig levels also had an effect in the same direction. Finally, the slight clock skew also worked in the same direction. So with that taken into account, the STA reports this: 

I now measure 2.784 ns. This means that I reach the fastest model, so I'm within the envelope. I still think it is a bit strange that my measurement corresponds to the 0C model when I know for a fact that the die temperature is around 70C, but the differences are small. A 100 ps offset in calibration would explain it fully.

I think we can leave it at that.