Test stimulus for FPGA validation

The tools you mention are all for on-chip debugging with the design running in hardware. This seems to be what you want to do.

If you are saying you want to toggle internal signals while the design is running, then ISSP is what you want. You can use it along with Signal Tap to see more high-speed signaling as you toggle signals (ISSP probe data is only available as fast as the JTAG connection). You can set up a Signal Tap trigger based on the ISSP source toggling or anything else that should be happening while the design is running.

In-System Memory Content Editor is for viewing and editing the contents of on-chip RAM blocks during runtime. That doesn't seem like what you want.