Forum Discussion
Vishnu_Ajith
New Contributor
New ContributorSynthesis error
I generated HDL file from qsys and did the compilation in Quartus. Following error log was found: Error(13224): Verilog HDL or VHDL error at altpcieav_256_rp_rxm_rdwr.sv(287): index 3 is out of rang...
sstrell
Super Contributor
Super ContributorSo are you saying that this did compile successfully at one point and now it doesn't?
And what does simulation have to do with this? Are we talking about compiling in Quartus or compiling for simulation in a simulation tool like Questasim?
