Forum Discussion
SivaKona
Occasional Contributor
Occasional Contributorpcie gen3x8 DMA EndPoint with HPTXS path is not meeting timing
Hi , I have generated an FPGA model with PCIe DMA EP and onchip Memory as shown in the attached "DMA_EP_OnchipMem_model.png" file. I have instantiated an Onchip Memory of size 16MB. Seeing Setup...
You may try to lower your clock frequency, with increased in clock period, it is easier to meet setup.
Or you can add pipeline stages. You may checkout the video below
https://www.youtube.com/watch?v=g6SjVhVderc
SivaKonaOccasional Contributor
Occasional ContributorI realized that the longer IC (Inter Connection) delays are due to the paths to farther Block RAMS blocks.
When I reduced OnChip memory size from 16MB to 2MB , The design met Setup time.
Is there a way close timing without reducing the Block RAM usage?
Regards
Siva Kona
