MAX V 5M*** and MAX II -- Examine - Verify Failure

Hello
and first of all thank you for your help and the information.
Based on this information I have tested with a new approach.

I can confirm the following:
1. a blank check is successfully displayed for an empty UFM/CFM
2. a Verify is successfully displayed for an empty UFM without security bit
3. a Verify error is displayed for an empty CFM without a security bit = normal

4. a blank check error is displayed for a loaded CFM without a security bit
5. a Verify successful is displayed for a loaded CFM without a security bit

6. a blank check error is displayed for a loaded CFM with security bit
7. a Verify error is displayed for a loaded CFM with security bit

Conclusion ----- there is no display or information in Quartus that a security bit is set - or that the CFM is protected by a security bit
You can only recognize the set security bit by the fact that the chip is not blank and that the Verify shows an error after being read out.

In my case, this means:
1: The first error I made is confirmed by the fact that I carried out the tests with an erased chip.
Here I was wrong in thinking that, similar to an EEprom (all FF), data of a CFM can also be read out and compared in the erased state.

2. the board to be repaired has the security bit set on the donor boards. Reading out the donor and repairing the defective boards is therefore impossible and they are electronic waste

Here a display in Quartus that a security bit is set would have been very helpful

Clear indications ( security set ) like cheap eprom software can do and display would have saved a lot of time and I would have expected this from a software as advanced as Quartus.