New Contributor
Frequent ContributorHi Chris,
Could you attach a simplified design that shows the error?
New Contributor@JonWay_C_Intel I have created and attached two configurations of a example project configured to run on the Intel Cyclone 10 LP Evaluation Kit.
one configuration showing the error message, and one showing that the settings rejected by quartus are valid (using on the fly reconfiguration to allow compliation with lower clock speed).
The example contains a description on how it is constructed and how to connect it as well as the resulting output waveforms.
Materials required:
EK-10CL025U256
Oscilloscope with >= 1Ghz bandwith & differential probe, 100 Ohm LVDS termination resistor, + 1 Single ended probe
Quartus Prime 20.1.0 Build 771 06/05/2020 SJ Lite Edition
Thank you for your support,
Chris
Frequent ContributorThanks for the design. I have a better idea now. You are trying to make a GPIO IO standard LVDS to toggle at 1GHz. It will message: Error (176060): The transmitter driving I/O pin pin_arduinobus_j7_4 at data rate 1000 Mbps exceeds the maximum allowed data rate of 740 Mbps for LVDS output
This is expected as the datasheet stated:
New Contributor@JonWay_C_Intel i was providing an example of the issue as you had requested in the simplest form possible. It was intended to show the error encountered, not the real application as this is a public forum and i cannot disclose the company's intellectual property in this manner.
To clarify: this error persists, independent of the toggle rate of the pin, as it is an issue with the quartus software deriving the real toggle rate and has nothing to do with the datasheet specification. To highlight this i have modified the example to a division factor of 4, now delivering instead of 500Mhz (=1Gbps) as before an output rate of 250MHz (=500Mbps) which is well within the datasheet specification. You can modify this to any arbitrary division factor, the issue will persist no matter how low you make the toggle rate of the pin:
output within spec - quartus does not allow to compile this
I have attached the modified examples:
1) version failing during the fitting process "correct implementation of the PLL parameters"
2) successfully compilable "dynamic pll workaround"
These represent the equivalent counterparts to the previous examples:
1) "Config_TestProgram - Not working (1GHz PLL intitial)" (08-28-2020 01:06 PM)
2) "Config_TestProgram - Working (500MHz PLL initial)" (08-28-2020 01:06 PM)
If you wish to have a look to the actual application causing this problem, please provide me a means to contact you in a non-public fashion to exchange the data and / or arrange the potential shipment of the demonstation hardware.
Thank you,
-Chris
New Contributor@JonWay_C_Intel i was providing an example of the issue as you had requested in the simplest form possible. It was intended to show the error encountered, not the real application as this is a public forum and i cannot disclose the companys intellectual property in this manner.
To clarify: this error persists, independent of the toggle rate of the pin, as it is an issue with the quartus software deriving the real toggle rate and has nothing to do with the datasheet specification. To highlight this i have modified the example to a division factor of 4, now delivering instead of 500Mhz (=1Gbps) as before an output rate of 250MHz (=500Mbps) which is well within the datasheet specification. You can modify this to any arbitrary division factor, the issue will persist no matter how low you make the toggle rate of the pin:
I have attached the modified examples:
1) version failing during the fitting process "correct implementation of the PLL parameters"
2) successfully compilable "dynamic pll workaround"
These represent the equivalent counterparts to the previous examples:
1) "Config_TestProgram - Not working (1GHz PLL intitial)" (08-28-2020 01:06 PM)
2) "Config_TestProgram - Working (500MHz PLL initial)" (08-28-2020 01:06 PM)
If you wish to have a look to the actual application causing this problem, please provide me a means to contact you in a non-public fashion to exchange the data and / or arrange the potential shipment of the demonstation hardware.
Thank you,
-Chris
New Contributor<message corrupted - please delete>
New Contributor@JonWay_C_Intel i was providing an example of the issue as you had requested in the simplest form possible. It was intended to show the error encountered, not the real application as this is a public forum and i cannot disclose the company's intellectual property in this manner.
To clarify: this error persists, independent of the toggle rate of the pin, as it is an issue with the quartus software deriving the real toggle rate and has nothing to do with the datasheet specification. To highlight this i have modified the example to a division factor of 4, now delivering instead of 500Mhz (=1Gbps) as before an output rate of 250MHz (=500Mbps) which is well within the datasheet specification. You can modify this to any arbitrary division factor, the issue will persist no matter how low you make the toggle rate of the pin:
I have attached the modified examples:
1) version failing during the fitting process "correct implementation of the PLL parameters"
2) successfully compilable "dynamic pll workaround"
These represent the equivalent counterparts to the previous examples:
1) "Config_TestProgram - Not working (1GHz PLL intitial)" (08-28-2020 01:06 PM)
2) "Config_TestProgram - Working (500MHz PLL initial)" (08-28-2020 01:06 PM)
If you wish to have a look to the actual application causing this problem, please provide me a means to contact you in a non-public fashion to exchange the data and / or arrange the potential shipment of the demonstation hardware.
Thank you,
-Chris
P.S.: My appologies for the many posts/edits of this message - something went wrong while updating it to correct a spelling mistake and the post disappeared...
