Forum Discussion
New ContributorError ID 18694: Still not resolved ???
- Hi,
hard to believe that you need to refer to weird workarounds like this...
Check your private message folder.
Regards,
Frank
New ContributorHi,
We are migrating an Arria 10 project from Quartus Prime Pro 17.1 to 24.1 and are currently blocked by Error (18694) related to the LVDS SERDES reference clock source.
The design uses a transceiver reference clock through HSSIREFCLKDIVIDER, which then drives external IOPLLs for LVDS TX banks. The same board and clock topology work correctly in Quartus 17.1, but Quartus 24.1 rejects the reference clock path during Fitter.
We have already tried using external PLLs, assigning the PLLs to the corresponding LVDS banks, as well as GLOBAL_CLOCK and REFCLK_FROM_CORE, but Error 18694 still remains.
We found references in the Altera Community indicating that there is an undocumented quartus.ini setting that can be used to bypass or relax this LVDS SERDES reference clock enforcement.
Could you please provide the corresponding quartus.ini setting or the recommended workaround for Quartus Prime Pro 24.1?
Device: Arria 10
Quartus version: Quartus Prime Pro 24.1
Error: 18694
Thanks.
Super ContributorHi EVAN
This had been sync internally that this is not a bug. The LVDS receiver all mode including Soft-CDR cannot have reference clock cross I/O bank. There's confusion at the document for user and update to the document is in the process. By the way, the Soft-CDR mode uses DPA block as well.
