Can Avalon-MM Slave BFM Intel FPGA IP be used to implement a memory block?

The "Avalon Verification IP Suite: User Guide" mentions a memory_mode on page 47:

"Response Generator and Data Cache— In memory_mode the Slave BFM models a single port RAM. A write operation stores the data in an associative array and generates no response. A read operation fetches data from the array and drives it on the response side of the Avalon interface. This mode simplifies loopback testing. "

However, there is absolutely nothing with this name anywhere outside this document. I have done a search of the .sv file of the BFM. I have not found anything there. Is this some sort of mistake?