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pnp's avatar
pnp
Icon for New Contributor rankNew Contributor
4 years ago
Solved

Bus index reversal when SystemVerilog module instantiates a BDF in Quartus Prime Pro 21.2

I have a legacy BDF that I need to use in a current design. Using Quartus Prime Pro v20.4 or v21.2, I see the bus indexes reversed on the port connections when the BDF diagram is instantiated from wi...
  • sstrell's avatar
    sstrell
    4 years ago

    Yeah, I'd just convert to HDL and use that if you have more complex designs causing this issue. Just save yourself the time and effort trying to fix the schematics.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
4 years ago

When I disconnected from both PRN and CLRN, the code for the register was correct. See attached. Maybe something else is going on for you. Check to make sure there aren't any little wire segments hidden behind the register in the schematic. Any little connection can cause an issue. It's why I'm not a fan of the schematic editor. Or maybe that's not the standard DFF primitive which would just throw everything out of whack (though you say this happens even without a register). I'm not sure what's going on then.

pnp's avatar
pnp
Icon for New Contributor rankNew Contributor
4 years ago

I agree with your sentiment about these schematics, and I can't wait to be completely rid of them. I don't think there are any extra wire bits in the .bdf. I opened it in Quartus II 9.1 SP2--that's all I have installed that can generate BDF->HDL--and generated a Verilog HDL file for it. Quartus 9.1 created a compact, correct representation for it:

// PROGRAM		"Quartus II"
// VERSION		"Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Full Version"
// CREATED		"Tue Aug 31 08:30:37 2021"

module bdftest(
    clk,
    x_in,
    y_out
);

input	clk;
input	[7:0] x_in;
output	[7:0] y_out;
reg	[7:0] y_out;

always@(posedge clk)
begin
    begin
    y_out[7:0] = x_in[7:0];
    end
end

endmodule

If I instantiate that in my Quartus Prime Pro 21.2 project instead of the .bdf, I get a correct instantiation:

If I instantiate that same .bdf rather than the generated verilog file in my v21.2 project, I get reversed connections. One gotcha I ran into was that regardless of the files listed in the project, the generated HDL file would get picked up for synthesis rather than the BDF if it was left in the project directory.

Are you suggesting that as the workaround: generate the HDL for the .bdf from an old version of Quartus and use that in the project? I can give that a try.

Thanks,

Paul

Edit: attached the .bdf. Had to add a .txt extension to get the forum software to allow me to attach. This is further proof these schematic files are antiquated: you can't even post them to the forum as-is!