PElmNew Contributor7 years agoAutomatic use of internal block RAMs I'm translating code from Xilinx devices to Intel to see if we could switch to Altera FPGAs. Xilinx tools automatically translate VHDL memory operations to block-ram without need to use macros or co...Show More
Recent DiscussionsError (292014): Can't find valid feature line for core SLL_CA_HBC_T001_Hyperbus_Memory_Controller_10Agilex 5 – Critical HSSI Error in JESD204B Example DesignThe quartus license works with version 25.0 but not with version 17.0Error(23098) when using IPM_IOPLL on Agliex 7Timing analysis - long combinational path