Honored ContributorHi
I am using quartus II 7.1 version for the first time and when i tried to compile my bdf design i am getting the below stated error which says that the name of the bus desclared is illegal cud some one help me out in this .... Error Error: Illegal wire or bus name "regsig3(33..0)" of type signal
Honored ContributorTry not to end busses with a number.
If you really like the name you have, then rename it as follows: regsig3_bit I have seen many tools get hung up this, as the expansion can make other similar names colide. AvatarHonored ContributorI think the parentheses are wrong too, as they should be square brackets. (I understand the urge to end signals with a number, so maybe add an underscore after it, like regsis3_[33:0], and that should hopefully work.)
