Altera_Forum
Honored Contributor
16 years agoRapid recompile
Anybody tried the rapid recompile feature in Quartus 9.1?
With rapid recompile feature switched on: I took a unpartioned flat design on an 80% full EP4SGX230 Stratix device and ran it through and it took 1hr 42min. I then changed the reset value from '0' to '1' in the vhdl for just one register and ran it though again. This time it took 1hr 36min. Not what I was hoping, although hardly conclusive on just one design. Am I missing something? I'd be glad to hear of anyones experiances with this feature.