Rapid recompile

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Anybody tried the rapid recompile feature in Quartus 9.1?

With rapid recompile feature switched on:

I took a unpartioned flat design on an 80% full EP4SGX230 Stratix device and ran it through and it took 1hr 42min. I then changed the reset value from '0' to '1' in the vhdl for just one register and ran it though again. This time it took 1hr 36min.

Not what I was hoping, although hardly conclusive on just one design.

Am I missing something?

I'd be glad to hear of anyones experiances with this feature.

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Hi Witty,

what did you mean with "rapid recompile feature " ?

Smart recomple or partition based design ?

Kind regards

GPK

No its not smart recomple or partitioning it's the new feature on Quartus 9.1.

http://www.altera.com/products/software/quartus-ii/whats-new/swf-qts-whats-new.html?gsa_pos=2&wt.oss_r=1&wt.oss=rapid%20recompile

I set it using...

set_global_assignment -name RAPID_RECOMPILE_MODE 
COMPATIBLE_PLACEMENT

I've found it to be of little use, unless I'm doing something wrong.

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No its not smart recomple or partitioning it's the new feature on Quartus 9.1.

http://www.altera.com/products/software/quartus-ii/whats-new/swf-qts-whats-new.html?gsa_pos=2&wt.oss_r=1&wt.oss=rapid%20recompile

I set it using...

set_global_assignment -name RAPID_RECOMPILE_MODE 
COMPATIBLE_PLACEMENT

I've found it to be of little use, unless I'm doing something wrong.

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Hi Witty,

I was not aware of this new feature, but I can imagine how it works. The feature could only work in case that Quartus found a lot of nodes which does not change. I'm pretty sure that changing the input value of the reset will cause a lot of changes in your FPGA implementation. I would try a change which influenced only a small portion of your design (e.g reduce the number of bits of a counter)

Kind regards

GPK

Pletz,

Think you may have hit the nail on the head so to speak. I considered the change I made to be trivial but in fact, as you say, it could have a big impact on the rest of the logic.

I'll think of something the is 100% trivial and try again.

Witty

Also note rapid recompile seems to turn of timing driven synthesis, which for my design was a real problem.

Took a while to notice that message in amongst the thousands of others useless warning and info messages that get dumped out.

I did see about a 25-30% compile time improvement, but the design never meet my timing requirements :(

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Do the older devices such as ArriaGX not support this feaure?!

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Hi Jerry,

the feature is not supported for ArriaGX.

Kind regards

GPK

I tried the Rapid Recompile option on a Cyclone III project recently.

I did a full recompile of the project which took about 8 minutes. I then turned on Rapid Recompile and changed one comparison in a line of verilog. The recompile then took 9 minutes.

I was far from impressed...

I am a member of Altera's SW department and I'd like to thank everyone for their comments on the Rapid Recompile feature that was introduced in Quartus II 9.1. Altera is committed to improving the quality and experience of this flow and we expect the Rapid Recompile behavior in Quartus II 10.0 to be much better. At this time, I cannot provide exact details, since Quartus II 10.0 has not been publicly announced.

Here are some comments on the feature:

1) Rapid Recompile is only supported for newer device families: Stratix III, Cyclone III, Stratix IV (GX/GT/E), Arria II GX, and Cyclone IV (GX/E). It is not supported for older FPGA device families nor for any HardCopy device family.

2) IMPORTANT: Users will only see the effects of Rapid Recompile after a full compilation (through the fitter) has been performed with the Rapid Recompile feature enabled. Users that compile once with Rapid Recompile off and then compile again with Rapid Recompile on will see no benefit.

- If the info message "Fitter has failed to locate previous placement information", Rapid Recompile will provide no compile time benefit.

- The "Incremental Compilation Preservation Summary" section in the fitter report will provide details about the placement & routing preservation for your design.

3) As mentioned by various users, in Quartus II 9.1, Rapid Recompile disables several optimizations (such as timing driven synthesis and beneficial skew optimization). With the exception of physical synthesis, all synthesis & fitter optimizations will work with Rapid Recompile in the Quartus II 10.0 release.

4) Rapid Recompile will have less impact for very small designs (e.g. <10 minutes). In Quartus II 9.1, Rapid Recompile accelerates the placement and routing operations. For small designs, the compilation time is not dominated by these tasks, so the upside for Rapid Recompile is bounded.

5) The performance of Rapid Recompile is largely dependent on whether the Quartus tool believes the change is "small". If the Quartus tool believes that the design change is "large", Rapid Recompile will disengage and the user will not see any compile time savings.

- As mentioned in this thread, a "small" change from the user's perspective may be perceived as a "large" change by the tool. Altera is working on techniques to ensure that, for Rapid Recompile, the tool recognizes "small" user changes as "small" design changes.

- Applying extensive, global optimizations to a "small" user change may be needed to obtain optimal performance. The user needs to be aware of their objectives and select the right flow to achieve their end goals. Rapid Recompile is focused on compile time reductions and timing preservation.

Please let me know if you have additional comments or questions about the Rapid Recompile feature.

- Mark