Honored Contributor
Honored ContributorHi Tom,
If you have an Altera Nios II kit development board, one idea you may want to try is to take one of the example designs that can with the Nios II kit and download that design to the board to make sure all the physical connections are working between the USB-blaster and the board. The example design already has a .SOF file provided so all you have to do is program the FPGA (this will eliminate the SOPC builder from the equation) and then run a simple program in the IDE. Location of the Altera development board example designs: C:\altera\71\nios2eds\examples\verilog C:\altera\71\nios2eds\examples\vhdl If the simple program fails then I would either suspect problem with the IDE's connection to the JTAG server to the board since the provided example SOF has already been tested on the development board by Altera. If that works, then you can try downloading your design to the board next to see what happens. If you get the failure with your downloaded hardware design, then you have an example design that you can pass to Altera support to replicate the problem and they can find a fix to the issue since they can take the design file you have and replicate the bug on their own development board. If you have a custom board, it should be simple to test a portion of your design on one of their development boards to at least determine if it might be an issue of the JTAG connection (i.e. noise or ringing on the trace) on a custom board. I hope this helps, Regards, -ATJ