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Altera_Forum's avatar
Altera_Forum
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16 years ago

ramstyle attribute in Quartus synthesis

I am trying to create some verilog that will receive a message with a set of sample data from a Nios processor and send the samples out on digital i/o pins sequentially. The message size is 512 bytes...
Altera_Forum's avatar
Altera_Forum
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16 years ago

i agree with starting from Quartus II templates or the Recommended HDL Coding Styles manual. if you deviate too much from the template all of the features may not be inferred. for example i just noticed on one of my designs that the M9K's output registers are not being used, so i will have to simplify my code or maybe just use the explicit template and keep my logic in a higher level file.

there was also a post about RAM coding styles on comp.arch.fpga today.