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Altera_Forum's avatar
Altera_Forum
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16 years ago

ramstyle attribute in Quartus synthesis

I am trying to create some verilog that will receive a message with a set of sample data from a Nios processor and send the samples out on digital i/o pins sequentially. The message size is 512 bytes...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

All FPGA internal RAM blocks are dual-ported, so you can basically access two locations simultaneously. But there are additional requirements to allow RAM inference. So it's best to start with Quartus editor templates for RAM inference and modify them stepwise according to your requirements.