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Altera_Forum's avatar
Altera_Forum
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16 years ago

ramstyle attribute in Quartus synthesis

I am trying to create some verilog that will receive a message with a set of sample data from a Nios processor and send the samples out on digital i/o pins sequentially. The message size is 512 bytes...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Thanks for all the responses.

I think I understand the problem now. Am I right in thinking that if I had only accessed one location in act_message[] per clock cycle then it would have been implemented in RAM?