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Altera_Forum's avatar
Altera_Forum
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16 years ago

ramstyle attribute in Quartus synthesis

I am trying to create some verilog that will receive a message with a set of sample data from a Nios processor and send the samples out on digital i/o pins sequentially. The message size is 512 bytes...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Also, don't forget when you have your Verilog/VHDL file open in Quartus, go to Edit -> Insert Template. They've got templates for RAMs that you can look at or paste directly into your code. I also like this a lot for the altera attributes and synthesis attributes.

(But Sanmao nailed the problem on why synthesis won't infer it to begin with)