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Not knowing Verilog
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That's excadtly the point. Although
always @ (posedge clk or negedge reset_n) may look strange to a VHDL programmer, it's correct synthesizable Verilog syntax. It's simply the equivalent of the VHDL construct
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if reset_n ='0'
elsif rising_edge(clk)
end if;
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You may want to take a look a the Quartus Verilog templates to get an idea of it,
The "ignoring ramstyle" problem is rather obvious from this lines
samples_to_send <= {act_message, act_message, act_message, act_message};
clocks_per_sample <= 50*({act_message, act_message, act_message, act_message});
They would already require an 8-port RAM, because 8 values are read simultaneuosly.
Honored Contributor
