ramstyle attribute in Quartus synthesis

Hi Bras0463,

in VHDL as well as in Verilog, Quartus will synthesize a ram block that is actually used as a normal ram (in: address, in & out: data). It will normally use on-chip block ram for that.

In your description however you are using specific addresses to your act_message ram. This is illustrated (marked in red) in the code-snippet below:

--- Quote Start ---

        ...
        begin
            // Complete message received
            byte_counter         <= 0;
            samples_to_send     <= {act_message, act_message, act_message, act_message};
            clocks_per_sample     <= 50*({act_message, act_message, act_message, act_message});    // Minimum sample time = 50 clock cycles = 1uS
            // Start sending output samples
            clock_counter         <= 0;
            samples_sent        <= 0;
            dio_output_sequence_state <= STATE_OUPUTTING;
        end
        ...

--- Quote End ---

Remember designing hardware is NOT like writing software!

When you use specific indices to your hardware like act_message[10] it means that the harware always needs access with wires from this memory location. This is also true for other memory addresses with specific indexes. There is no way that you will have instantaneous access to several different places in your memory when you would only be able to use an on-chip block RAM. Therefore Quartus correctly synthesizes a ram based on LE's. This is only to enable the access to the words on different addresses.

To solve this problem you should define a multiplexor as input to the address of your act_message RAM. Depending on the control signals of your multiplexor you will be able to determine what word you want to read at a specific time. At that time Quartus will also automatically be able to infer an on-chip block RAM.

Hope this helps...