ramstyle attribute in Quartus synthesis

Hi,

Not knowing Verilog, something did strike me as odd in your code. Your always process is defined as:

always @ (posedge clk or negedge reset_n)

It seems like you want the process to trigger on a rising clock edge or a falling reset_n edge. Normally you want the process to trigger on the clock edge and on the reset level. Having two edges like this is generally not synthesizable - or at least not to the logic you intended. I may just be advertising my ignorence, and maybe this is the way you specify it in Verilog, it just lokked odd to me.

Regards,

Niki