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Altera_Forum's avatar
Altera_Forum
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16 years ago

ramstyle attribute in Quartus synthesis

I am trying to create some verilog that will receive a message with a set of sample data from a Nios processor and send the samples out on digital i/o pins sequentially. The message size is 512 bytes...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Hi,

Unfortunately I do not know Verilog well, but the more typical way of using a RAM would be to instantiate a RAM component. You can do this with the Plug-In Megawizard, or by hand if you know the model name and parameters.

There has been a post some time ago about the ability of Quartus to recognise a RAM from behavoural code and then to automatically instantiate a RAM component, but that was for VHDL. Your syntax needs to be correct for the compiler to recognise the RAM. Personally I prefer to instantiate the RAM component explicitly since then I have control over the use of my RAM resources.

Regards,

Niki