RAM property help

hi，

I use the wizard to generate most of the ram and port map to it. the only ram i did not directly use wizard is the one with mif file. There are 64 of them with different mif file. But I just copy the code and edit the mif file name only.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY mem_0 IS
   PORT
   (
      address_a      : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
      address_b      : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
      clock      : IN STD_LOGIC  := '0';
      data_a      : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
      data_b      : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
      rden_a      : IN STD_LOGIC  := '1';
      rden_b      : IN STD_LOGIC  := '1';
      wren_a      : IN STD_LOGIC  := '0';
      wren_b      : IN STD_LOGIC  := '0';
      q_a      : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
      q_a      : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
   );
END mem_0;
ARCHITECTURE SYN OF mem_0 IS
   SIGNAL sub_wire0    : STD_LOGIC_VECTOR (31 DOWNTO 0);
   SIGNAL sub_wire1    : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
   q_a    <= sub_wire0(31 DOWNTO 0);
   q_b    <= sub_wire0(31 DOWNTO 0);
   altsyncram_component : altsyncram
   GENERIC MAP (
      address_reg_b => "CLOCK0",
      clock_enable_input_a => "BYPASS",
      clock_enable_input_b => "BYPASS",
      clock_enable_output_a => "BYPASS",
      clock_enable_output_b => "BYPASS",
      indata_reg_b => "CLOCK0",
      init_file => "router_0_init_data.mif",  ----------- I only edit this line for diff mif file name 
      intended_device_family => "Stratix V",
      lpm_type => "altsyncram", 
      numwords_a => 128,
      numwords_b => 128,
      operation_mode => "BIDIR_DUAL_PORT",
      outdata_aclr_a => "NONE",
      outdata_aclr_b => "NONE",
      outdata_reg_a => "CLOCK0",
      outdata_reg_b => "CLOCK0",
      power_up_uninitialized => "FALSE",
      ram_block_type => "M20K",
      read_during_write_mode_mixed_ports => "DONT_CARE",
      read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
      read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
      widthad_a => 7,
      widthad_b => 7,
      width_a => 32,
      width_b => 32,
      width_byteena_a => 1,
      width_byteena_b => 1,
      wrcontrol_wraddress_reg_b => "CLOCK0"
   )
   PORT MAP (
      address_a => address_a,
      address_b => address_b,
      clock0 => clock,
      data_a => data_a,
      data_b => data_b,
      rden_a => rden_a,
      rden_b => rden_b,
      wren_a => wren_a,
      wren_b => wren_b,
      q_a => sub_wire0,
      q_b => sub_wire1
   );
END SYN;

The above is what I have for the ram with .mif file. Then I use matlab to print these code 64 time with different mif file name. Is there anything wrong with it?

Currently I am not sure which memory is fitted to logic cell, but other rams I have is directly port map to the wizard generated component, thus I think the above one might be the one using logic cell.

Is there any way I can check which ram is generated by logic cell? Does Quartus have this function?

many thanks for the help.