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Altera_Forum
Honored Contributor
Honored ContributorRAM property help
Hi all, I have a question about using on chip ram. According to what I read from the quartus handbook, the port input (e.g. address, input data) to a RAM should be clocked in order to let softw...
Altera_ForumHonored Contributor
Honored ContributorHi,
I am writing a sorting network with 64 nodes and 5 RAMs in each node, but according to the compiling result, some of the RAMs is fitting using logic cell but not on chip memory which reduce the performance a lot. According to the compiling report, there is 64 RAMs which is compiled using logic cell. After I do some search about the problem, it seems the unclocked input may cause this problem, thus I just wondering if my compare and and input to m2 process have this unclocked problem. If not, I may need to look at other place of the code. Is there any way I can check which RAM is fitting to logic cell but not on chip memory? Thanks for the help.
