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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

ram megafunction

would like to use the altsyncram megafunction.

When a ram block is defined as:

module ram_64x20 (

clock,

wren,

rden,

address,

wrdata,

rddata

);

input clock;

input wren;

input rden;

input [5:0] address;

input [19:0] wrdata;

//************************************************** ***************************

// Regs

output reg [19:0] rddata;

reg [19:0] mem [0:63]/* synthesis syn_ramstyle="block_ram"*/;

it gets mapped to the ram megafunction, but this ram block does not:

module ram_512x32_en (

clock,

wren,

rden,

address,

byteena,

wrdata,

rddata

);

input clock;

input wren;

input rden;

input [8:0] address;

input [3:0] byteena;

input [31:0] wrdata;

//************************************************** ***************************

// Regs

output reg [31:0] rddata;

reg [31:0] mem [0:511]/* synthesis syn_ramstyle="M9K, no_rw_check"*/;

Is there a way to get the quartus tool to map this using the ram megafunction ?

Thanks

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Well you failed to mention which device family you are using. Also, you left out the implementation of the RAM. However, the following seemed to work fine for a Cyclone III device:

    module test(
        input           clock,
        input           wren,
        input           rden,
        input      address,
        input      byteena,
        input     wrdata,
        output  reg   rddata
        );
    // Regs
    reg  mem /* synthesis syn_ramstyle="M9K, no_rw_check"*/;
    always @(posedge clock) begin
        if(wren & byteena)   mem <= wrdata;
        if(wren & byteena)   mem <= wrdata;
        if(wren & byteena)   mem <= wrdata;
        if(wren & byteena)   mem <= wrdata;
    end
    always @(posedge clock)
        if(rden)    rddata  <= mem;
    endmodule

    Jake