ram megafunction

Well you failed to mention which device family you are using. Also, you left out the implementation of the RAM. However, the following seemed to work fine for a Cyclone III device:

module test(
    input           clock,
    input           wren,
    input           rden,
    input      address,
    input      byteena,
    input     wrdata,
    output  reg   rddata
    );
// Regs
reg  mem /* synthesis syn_ramstyle="M9K, no_rw_check"*/;
always @(posedge clock) begin
    if(wren & byteena)   mem <= wrdata;
    if(wren & byteena)   mem <= wrdata;
    if(wren & byteena)   mem <= wrdata;
    if(wren & byteena)   mem <= wrdata;
end
always @(posedge clock)
    if(rden)    rddata  <= mem;
endmodule