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SAbde7
Occasional Contributor
Occasional ContributorRAM block failing timing at 320Mhz
I am using the DE5-net kit(Stratix V). There is a RAM block in my design that is being clocked with 400 Mhz(only as a test. I actually want to go higher). Paths inside the RAM block (between porta_we...
SAbde7Occasional Contributor
Occasional ContributorIt turns out the failing path was not internal but a loop through outside logic back to an internal register. It was hard to tell from the source and destination registers(their names are misleading). I have added constraints to the project to try to target this path and it seems to be working with over 400 MHz now, though I get other strange timing failures for other paths when I try to go higher, which I will probably ask about in another thread.
