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SAbde7's avatar
SAbde7
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

RAM block failing timing at 320Mhz

I am using the DE5-net kit(Stratix V). There is a RAM block in my design that is being clocked with 400 Mhz(only as a test. I actually want to go higher). Paths inside the RAM block (between porta_we...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
6 years ago

Can you post your .sdc, the detailed timing report and perhaps the code implementing the memory?

That's pretty fast for a Stratix V design.

#iwork4intel