RAM 1-port mega function - Single Port Ram module

After eating enough rice and beans and read with enough attention the following documents:

http://quartushelp.altera.com/13.0/mergedprojects/hdl/mega/mega_file_altsynch_ram.htm

RAM Megafunction User Guide v2.0 2007.pdf

I got a solution to my problem posted here.

I'm building a TRS80 using the Quartus II design the graphic (block file / schematic diagram).

And I'm keeping the old fashioned diagramming, not using closed buses and closed blocks.

I'm posting below how was the result of the code to the RAM memory,

in my case, will be a 2114 (1k x 8) and the image of its symbol.

I hope this helps someone with the same difficulties as I had.

-- ============================================================
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram 
-- File Name: RAM.vhd
-- Megafunction Name(s): altsyncram
-- Simulation Library Files(s): altera_mf
-- ============================================================
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY RAM IS
 PORT(
  A0  : IN STD_LOGIC;
  A1  : IN STD_LOGIC;
  A2  : IN STD_LOGIC;
  A3  : IN STD_LOGIC;
  A4  : IN STD_LOGIC;
  A5  : IN STD_LOGIC;
  A6  : IN STD_LOGIC;
  A7  : IN STD_LOGIC;
  A8  : IN STD_LOGIC;
  A9  : IN STD_LOGIC;
  D7  : INOUT STD_LOGIC := 'Z';
  D6  : INOUT STD_LOGIC := 'Z';
  D5  : INOUT STD_LOGIC := 'Z';
  D4  : INOUT STD_LOGIC := 'Z';
  D3  : INOUT STD_LOGIC := 'Z';
  D2  : INOUT STD_LOGIC := 'Z';
  D1  : INOUT STD_LOGIC := 'Z';
  D0  : INOUT STD_LOGIC := 'Z';
  CLK : IN STD_LOGIC := '1';
  CS  : IN STD_LOGIC := '1';
  RW  : IN STD_LOGIC := '1'
 
--  address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
--  clock  : IN STD_LOGIC  := '1';
--  data  : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
--  rden  : IN STD_LOGIC  := '1';
--  wren  : IN STD_LOGIC ;
--  q   : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
 );
END RAM;
ARCHITECTURE SYN OF ram IS
 SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
 SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
 COMPONENT altsyncram
 GENERIC(
  clock_enable_input_a    : STRING;
  clock_enable_output_a   : STRING;
  intended_device_family   : STRING;
  lpm_hint        : STRING;
  lpm_type        : STRING;
  numwords_a       : NATURAL;
  operation_mode      : STRING;
  outdata_aclr_a      : STRING;
  outdata_reg_a      : STRING;
  power_up_uninitialized   : STRING;
  read_during_write_mode_port_a : STRING;
  widthad_a       : NATURAL;
  width_a        : NATURAL;
  width_byteena_a     : NATURAL
 );
 
 PORT(
  address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
  clock0  : IN STD_LOGIC ;
  data_a  : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
  wren_a  : IN STD_LOGIC ;
  q_a   : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
  rden_a  : IN STD_LOGIC 
 );
 END COMPONENT;
BEGIN
-- q <= sub_wire0(7 DOWNTO 0);
   (D7,D6,D5,D4,D3,D2,D1,D0) <= sub_wire0(7 DOWNTO 0) when ((CS = '0') AND (RW = '1')) else std_logic_vector'("ZZZZZZZZ");
   sub_wire1(7 DOWNTO 0) <= (D7,D6,D5,D4,D3,D2,D1,D0) when ((CS = '0') AND (RW = '0')) else NULL;
 altsyncram_component : altsyncram
 GENERIC MAP(
  clock_enable_input_a    => "BYPASS",
  clock_enable_output_a    => "BYPASS",
  intended_device_family    => "Cyclone IV E",
  lpm_hint        => "ENABLE_RUNTIME_MOD=NO",
  lpm_type        => "altsyncram",
  numwords_a        => 1024,
  operation_mode      => "SINGLE_PORT",
  outdata_aclr_a      => "NONE",
  outdata_reg_a       => "CLOCK0",
  power_up_uninitialized    => "FALSE",
  read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
  widthad_a        => 10,
  width_a         => 8,
  width_byteena_a      => 1
 )
 
 PORT MAP(
--  address_a => address,
  address_a => A9&A8&A7&A6&A5&A4&A3&A2&A1&A0,
--  clock0  => clock,
  clock0  => CLK,
--  data_a  => data,
  data_a  => sub_wire1,
--  wren_a  => wren,
  wren_a  => (NOT RW) AND (NOT CS),
--  rden_a  => rden,
  rden_a  => RW AND (NOT CS),
  q_a   => sub_wire0
 );
END SYN;

rmk: would also like to post a comment to something that I could not understand,

for not yet understand VHDL very well... (I left the original code annotated).

In the part that is in bold, I tried to use the following lines:

D7&D6&D5&D4&D3&D2&D1&D0 <= sub_wire0(7 DOWNTO 0) when ((CS = '0') AND (RW = '1')) else std_logic_vector'("ZZZZZZZZ");
sub_wire1(7 DOWNTO 0) <= D7&D6&D5&D4&D3&D2&D1&D0 when ((CS = '0') AND (RW = '0')) else NULL;

The second line works, but the first line not work. :(

Also, follows a memory image of the memory symbol.