Questions from a lab exercise.

Just update what I just tried. I feel I understand more than before, but still dunno what to do next. I hate my teachers now. Haha

What I added here is

+ Take rw signal from CPU, if rw = 1 that means write, and rw =0 that means read.

+ The mux here to control the data bus

+ The encoder to decide which signal receive commands from CPU( I think…:D)

+ So according to the encoder, we will get

If we wanna read from RAM, we choose address for RAM ( Ram_en will be 1), Sel =00; the data from RAM will connect to the data bus( I think)

The same for PORT A, Sel =01 when Port_En =1

Good news is I can compile it without any errors. Haha. Thanx for seeing my ques.