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Questions:
1. Should this block be synthesisable?
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no just testing
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Questions:
2. How "random" does it need to be?
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i want to generate 36 output values with only 1 input
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Questions:
I ask these questions because:
1. VHDL has a random number generator, but it is not synthesisable and only meant for testbenches
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would plz tell me about it, and if it take range or not??
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Questions:
2. Have you looked into a LFSR?
http://en.wikipedia.org/wiki/lfs with this you can create a pseudo random sequence. This would be the easiest logic solution. I have heard of others before but they often involve rlocs and require good knowledge on oscilators. One solution (i havent done it, but had it described) is to route a clock though some logic as far apart as possible. Then sample the clock at a given rate, to try and give a random bit (it was described to me a long time ago, so I may have some details wrong).
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the work arround i did was similar to LFSR..
execuse me, i couldn't get the rest of this..
thanks,
Niveen
Honored Contributor
