question regarding random number generator

Questions:

1. Should this block be synthesisable?

2. How "random" does it need to be?

I ask these questions because:

1. VHDL has a random number generator, but it is not synthesisable and only meant for testbenches

2. Have you looked into a LFSR? http://en.wikipedia.org/wiki/lfs with this you can create a pseudo random sequence. This would be the easiest logic solution. I have heard of others before but they often involve rlocs and require good knowledge on oscilators. One solution (i havent done it, but had it described) is to route a clock though some logic as far apart as possible. Then sample the clock at a given rate, to try and give a random bit (it was described to me a long time ago, so I may have some details wrong).