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Altera_Forum
Honored Contributor
Honored ContributorQuestion about True Dual Port RAM
Hello, I'am using True dual port ram one port for write and the other one for read. When i change the content of an address i get the output on the read port delayed by two cycles. ...
Altera_ForumHonored Contributor
Honored ContributorTo register input or output, you add registers to the pipeline in those input. That means putting the signals in a clocked process.
Your code (lifted I see from the quartus handbook) registers the input and output. As long as you register the read address then the Q output doesnt have to be registered.
