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Altera_Forum's avatar
Altera_Forum
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14 years ago

question about testbench

Hi all, I am trying to write a VHDL testbench. I am wondering what kind of file I should create for the testbench, VHDL script file or anything else? If it is VHDL script file, how does the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

There no such thing as a VHDL script file. a testbench is just a VHDL file. You instantiate the unit under test inside the testbench.