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Fpga_Egr_2025's avatar
Fpga_Egr_2025
Icon for Occasional Contributor rankOccasional Contributor
7 months ago

Questasim UVM macros

Hi , I am trying to compile and run simulation in Questasim , using uvm libraries and uvm packages. But i am getting error that include files not defined , although these uvm files are installed in...
Simulation
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
7 months ago

Try using below command with +incdir:

vlog -sv -work work +incdir+$UVM_HOME/src uvm_sim_pk.sv

Make sure $UVM_HOME points to your UVM installation directory.

example:

vlog -sv -work work +incdir+C:/<installation directory>/questa_fe/verilog_src/uvm-1.1d/src uvm_sim_pk.sv

Then vsim example:

vsim -c -sv_lib <installation directory>/uvm-1.1d/win64/uvm_dpi work.my_tb -do "run -all; quit"

You may checkout this webpage for further details:

https://blogs.sw.siemens.com/verificationhorizons/2011/03/08/using-the-uvm-10-release-with-questa/

Do note that the Questa Intel FPGA edition does not support advanced verification features such as randomization. You might see below error message:

# Error: Failure to checkout svverification license feature.

# Fatal: (vsim-7099) Unable to check out a verification license for the randomize() feature.

In that case, you might need to use back the Siemens Questa version. (not Intel/Altera version)

Regards,

Richard Tan

  • Fpga_Egr_2025's avatar
    Fpga_Egr_2025
    Icon for Occasional Contributor rankOccasional Contributor
    7 months ago

    Hi I tried to compile and include in the working directory , but no success in linking "uvm_macros.svh" .

    It is dependent on "uvm_tlm_imps.svh" , which vlog did not complain about , but when i tried to include "uvm_macros.svh" it refers to "uvm_tlm_imps.svh".

    Any clue what should be the compile order ? to fix this

    See image attached.

    Thanks

    Regards,