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GOMEZ_IT's avatar
GOMEZ_IT
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

Questasim INTEl EDITION counter simulation

Hello. I'm using this vhdl code to make an 8 bit counter with enable. Quetasim Intel fpga does not increment the counter regularly (defined as variable). It goes from 'X' to '1' and then it...
Simulation
  • roeekalinsky's avatar
    roeekalinsky
    2 years ago

    @GOMEZ_IT, I think you were right, this looks like a simulator problem.

    I was able to reproduce your original observation, and it appears to be a bug in older versions of Questa, up to the version shipped with Quartus Pro 23.3.

    The version of Questa shipped with Quartus Pro 23.4 doesn't appear to exhibit this symptom. Or at least not with this test case. But I don't know if this was a known bug that got fixed, or if the symptom just went away with other changes in Questa. That's something you should confirm with Intel and/or Mentor/Siemens.

    For ease of testing, I modified your test case slightly to be able to run in a more minimalist command line mode, with console messages in lieu of waveforms. See attached zip.

    Running this test case with all the simulators I currently have available to me I got the following results:

    • Questa from Quartus Pro 22.2: bad
    • Questa from Quartus Pro 22.4: bad
    • Questa from Quartus Pro 23.1: bad
    • Questa from Quartus Pro 23.2: bad
    • Questa from Quartus Pro 23.3: bad
    • Questa from Quartus Pro 23.4: good
    • Modelsim DE 2022.4: good
    • ghdl 4.0.0-dev: good

    See attached log.txt for the above results.

    -Roee

roeekalinsky's avatar
roeekalinsky
Icon for Contributor rankContributor
2 years ago

You're going wrong in using a variable declared in the process, whereas you should be using a signal declared in the architecture. As you have it coded, with every entry into the process, i.e. every clock cycle, your variable is getting reinitialized to zero and then incrementing by one.

GOMEZ_IT's avatar
GOMEZ_IT
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

But why if i invert 2 lines of code the simulation works?

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity COUNT8 is

port(

CLK : in std_logic;
EN : in std_logic;
DOUT : out std_logic_vector(7 downto 0)
);

end COUNT8;

architecture behavior of COUNT8 is

begin
-- notice the process statement and the variable COUNT
clk_proc:process(CLK)
variable COUNT:std_logic_vector(7 downto 0) := x"00";
begin
if rising_edge(CLK) then
if en = '1' then

DOUT <= COUNT;
COUNT := std_logic_vector((unsigned(COUNT)) + 1);

end if;
end if;
end process clk_proc;

end behavior;

  • roeekalinsky's avatar
    roeekalinsky
    Icon for Contributor rankContributor
    2 years ago
    @GOMEZ_IT wrote:

    But why if i invert 2 lines of code the simulation works?


    I'm surprised to hear that it does. I wouldn't think it should work in either case. Looks like it's time to dig into the VHDL LRM for clarification on the exact semantics of variable initialization in a process.