Occasional Contributor
Occasional ContributorWell, the script and the flow work 99.9% of the time. But every now and then I see a hang up of the simulator, without doing any changes to the VHDL files or the flow at all.
How can this behavior be caused by missing files or a bad flow? I mean, simulation is deterministic. I'd expect the same outcome on every run.
Occasional ContributorI'm now trying to create a Quartus project to run the simulation.
Analysis and synthesis works fine. But it seems that Quartus does not respect the correct compile order for the files when generating the Questa "*_run_msim_rtl_vhdl.do" script. The script tries to compile the architecture of a module before its entity which results in a compiler error.
(I moved the entity compilation call manually before the architecture compilation and it worked then.)
The file order in the QSF file is correct and the same as in "Settings -> Files". How can I force Quartus to keep this order when generating the Questa DO script?
