Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

QuartusII IBUF and OBUF delays

I'm using QuartusII 13.0sp1 and targeting device 5SGXEA7N2F45C2. For a successive run, I'm getting different IBUF and OBUF delays for the same path as shown in the attached screenshot.

Initally, I got the below delays.

0.353 ; RR ; CELL ; 1 ; IOIBUF_X62_Y0_N45

2.542 ; FF ; CELL ; 1 ; IOOBUF_X0_Y4_N49.

Then next run, I got the following.

0.535 ; RR ; CELL ; 1 ; IOIBUF_X62_Y0_N45

2.821 ; FF ; CELL ; 1 ; IOOBUF_X0_Y4_N49

What’s the reason/cause of these differences?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Was the runs under the same conditions: IE was the routing the same?

    Or was the temperature Skewed. (IE hot vs cold corners)?

    Without looking at the full report, I'm not sure I can answer, but I know voltage level, temperature, and line routing all are part of the timing calculations.

    Pete
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    This is a simple testcase where I'm working on closing timing on my output signals which for this testcase I used only 8 bits. For the timing with the less delay, I only had location constraints on input clock and dout[4]. Quartus auto-assigned the rest of the output pins and timing was met. In the next run, I assigned the rest of the dout pins to the same bank 3A as dout[4]. This is where I found the different delays on dout[4] IBUF and OBUF.

    Basically, I ran through initially and reviewed the timing reports. Then in Chip Planner I assigned the rest of the dout signals to Bank 3A and reran through the full flow.