Honored Contributor
Honored ContributorThis is a simple testcase where I'm working on closing timing on my output signals which for this testcase I used only 8 bits. For the timing with the less delay, I only had location constraints on input clock and dout[4]. Quartus auto-assigned the rest of the output pins and timing was met. In the next run, I assigned the rest of the dout pins to the same bank 3A as dout[4]. This is where I found the different delays on dout[4] IBUF and OBUF.
Basically, I ran through initially and reviewed the timing reports. Then in Chip Planner I assigned the rest of the dout signals to Bank 3A and reran through the full flow.
